Generally, conventional manufacturing methods of the thin film transistor are performed as followings: first, a semiconductor thin film for channels is formed flatly; second, a thin film transistor gate insulating layer and thin film transistor gate are formed over it; and lastly, a source/drain is formed by implanting impurities onto a portion of the semiconductor thin film.
However, when applying the above mentioned thin film transistor manufacturing technique to the manufacturing of a next generation highly integrated SRAM or LCD, the unit cell area increases greatly and as a result, the device size increases. That is why the above mentioned technique is not suited for manufacturing the highly integrated SRAM. Also, during the manufacturing process of the LCD requiring a high resolution, the unit area occupied by the thin film transistor must be minimized in order to upgrade the resolution. However, this objective can not be achieved by applying the conventional manufacturing technique of thin film transistor.